The high mobility of charge carriers in graphene combined with the ability to modulate the carrier concentration by an external electric field has made graphene-based field-effect transistors (GFETs) promising candidates for future high frequency applications. One of the critical factors limiting the ultimate performance of graphene FETs is the parasitic series resistance between the source/drain contacts and the gated graphene channel. While these access regions serve to reduce the parasitic capacitance between the gate and the source/drain electrodes, their resistance results in a lower current that hinders the device performance.